// +FHDR------------------------------------------------------------
//                 Copyright (c) 2022 .
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : spt_interface.sv
// Author        : 
// Created On    : 2022-08-25 15:10
// Last Modified : 
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

`ifndef __SPT_INTERFACE_SV__
`define __SPT_INTERFACE_SV__

`timescale 1ns/1ps

interface spt_interface(input clk, rst_n);

	logic 	        valid;
    logic [16 -1:0] data;

	clocking drv @(posedge clk);
		default input #1ps output #1ps;
		output	valid;
        output data;
	endclocking : drv
	modport pkt_drv (clocking drv);

	clocking mon @(posedge clk);
		default input #1ps output #1ps;
		input	valid;
        input data;
	endclocking : mon
	modport pkt_mon (clocking mon);

endinterface

`endif
